Files:
        APCB_MDN_D5.bin - Data only - No license, ABI or Version #
	TypeId0x55_SplTableBl_MDN_CHROME_RO.sbin - Data only, no license
	TypeId0x55_SplTableBl_MDN_CHROME.sbin - Data only, no license

2022-12-12: Initial release of the ChromeOS RO SPL table

SPL/SVN - Security Patch level / Security Version Number
A version number used to prevent Rollback attacks.
Software updates with an SVN lower than the currently installed SVN
are not permitted.

* Version: 3c.03.12
* Release Date: 2022-09-25
* Supported Silicon: AMD Mendocino
* Requirements/dependencies: None
* Errata: None

Versioned Chip Endorsement Key (VCEK) Certificate and KDS Interface
Specification
Document # 57230 Rev. 0.50 October 2021
https://web.archive.org/web/20221213033802/https://www.amd.com/system/files/TechDocs/57230.pdf


2022-09-27: Initial release of the ChromeOS RW SPL table

* Version: 3c.03.12
* Release Date: 2022-09-25
* Supported Silicon: AMD Mendocino
* Requirements/dependencies: None
* Errata: None

2022-09-02: Initial public release:
- Add APCB_MDN_D5.bin
    This is a data file that gives configuration data to AMD's ABL,
    the PSP AGESA Bootloader.  As there is no code, there is no ABI,
    license, or version number.

    Specified contents describing memory initialization:
    Memory is 2 channel, LPDDR5/LPDDR5x

    The GPIOs to use for the SPD identifiers:
    Bit 0: GPIO 144
    Bit 1: GPIO 85
    Bit 2: GPIO 79
    Bit 3: GPIO 91

   Contains 16 slots for possible SPD entries.
   UMA size is set to 64MB.
   eSPI I/O range address and size configuration.
   MEMRESTORECTL is enabled to leverage MRC Cache.

sha1sum:
a91237472d662b8035450e19f118adaece4748f4  APCB_MDN_D5.bin
e66c4ace7fa13913d2147016a7a0544b9f52de61  TypeId0x55_SplTableBl_MDN_CHROME_RO.sbin
c761d0c9386f302ea50fefd8762b1b4c85df117b  TypeId0x55_SplTableBl_MDN_CHROME.sbin
